The present invention relates in general to electronic circuits and, more particularly, to logic circuits.
A typical logic circuit, i.e. latch, gate, or buffer, has an input/output (I/O) standard for differential input or a single-ended input mode of operation. The logic circuit can be a circuit from a Complementary Metal Oxide Semiconductor (CMOS), Emitter Coupled Logic (ECL), or a Positive Emitter Coupled Logic (PECL) technology. The differential input device typically has a D input pin and a D bar input pin, both of which are external pins to the logic circuit. The D bar input is the complement of the D input. The single-ended input device typically has one input, D input, which is an external pin to the logic circuit. The D bar input of the single-ended input device is connected to a voltage reference corresponding to the single-ended input signal on the D input.
The differential input device has a differential signal received on the D input pin and its complement on the D bar input pin of the logic circuit. However, single-ended input devices only require one input for the single-ended input signal and as a result are typically used over differential input devices. For example, an ECL single-ended input device has an ECL single-ended input signal at the D input and a voltage reference of VBB connected external to the logic circuit at the D bar input. A typical VBB reference level used for a single-ended input device is centered around a conventional ECL voltage swing. However, the VBB reference level is only used for a single-ended input device receiving a single-ended input ECL signal. Thus, a voltage reference of VBB on the D bar input can create problems when not receiving an ECL input signal. For example, to receive a CMOS single-ended input signal on the D input of a single-ended input device a different voltage level is required at the D bar input. The VBB reference level connected to the D bar input when receiving a CMOS single-ended input signal on the D input provides an incorrect voltage reference. An additional connection, or a different device manufactured for CMOS single-ended input operation is typically needed to provide the necessary reference level for a CMOS single-ended input signal.
Thus, it is desired to have a logic circuit that can receive different single-ended input signals, i.e. ECL, CMOS, or PECL using only one device to resolve the above problems. The invention disclosed herein will address the above problems.